CPU Director settings? |
September, 06, 2003 7:17 AM |
brinster |
Trying to enable the L3 cache on my Sonnet G4 700 (PTPro). L2CacheConfig won't enable L3; had some trouble with X-Tuneup; so now I'm trying CPU Director. My problem is I don't know what settings to use for other variables in L3 control panel. I know it has a 1 MB cache at 200 mhz. But what about choices for... - backside cache type (MSU G2 DDR, Pipelined Synchronous (PB2), or Pipelined Late- Write)? - backside cache sample point (5, 4, 3 or 2 clocks)? - backside cache P-clock sample point (0, 1, 2, 3, 4, or 5 clocks)? I would like to get these right or close to right since I've had a freeze and a kernal panic on first two attempts to enable the L3 cache. |
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